Chapter 4

An American Megatrends, Inc. (AMI) system BIOS with embedded setup and hard disk setup utilities resides in Flash ROM on the board. Access the BIOS setup by pressing the DELETE key during system boot.

CMOS Battery
The SP has an internal battery that backs up the real time clock and CMOS memory.

The BC has eight LEDs arranged in two groups of four. As the system proceeds through its Power On System Test (POST) these LEDs display binary codes which can be used to diagnose board failures. The post codes can be found on the Cubix Customer Service Web Site at: http://www.cubix.com/support

All BC 5200TX system memory is provided in 72-pin, 36-bit standard 60ns SIMMs. Two SIMMs must be installed, and both SIMMs must be of an identical size. Tables 4-1 and 4-2 define the boards I/O configuration.

Memory Range	Size	Use
00000-9FFFF	640KB	Conventional Memory
A0000-AFFFF	64KB	VGA Graphics Buffer
B0000-B7FFF	32KB	MDA Text Buffer
B8000-BFFFF	32KB	VGA/CGA Text Buffer
C0000-C7FFF	32KB	VGA Bios
C8000-DFFFF	96KB	Available
E0000-FFFFF	127KB	System & PCI BIOS

ISA Ports	Description
0000-00FF	Various "AT" functions in ISP chip and keyboard controller
01F0-01F7	IDE hard drive interface
02F8-02FF	COM2
03A0	Cubix supervisory interface
03A8-03AF	IES serial port
03B4-03B5	VGA
03BC-03BF	LPT1
03C0-03CF	VGA
03D4-03D5	VGA
03F0-03F7	Floppy / IDE
03F8-03FF	COM1

The 16 system hardware interrupts on the SP are represented in Table 4 - 4. Interrupts are managed by two standard 8259A Programmable Interrupt Controllers (PICs). Interrupts at IRQ 0 through 7 are located on the main PIC; IRQ 8 through 15 are on the SLAVE PIC.

IRQ	Description	IRQ	Description
0	Timer clock	8	Real Time Clock
1	Keyboard	9	Redirected IRQ 2
2	Second OIC controller	10	Set By PCI Plug & Play at boot time
3	COM2	11	Set By PCI Plug & Play at boot time
4	COM1	12	Available (or PS/2 Mouse)
5	Set By PCI Plug & Play at boot time	13	Math Coprocessor
6	Floppy Disk Controller	14	Primary IDE Controller
7	LPT1	15	Secondary IDE Controller (or IES)

The SP has a PS/2 compatible keyboard controller with the AMI keyboard BIOS. The keyboard controller uses IRQ 1 for its interrupts, and requires no DMA channel. The keyboard controller also supports a PS/2 compatible mouse which uses IRQ 12. Switch S1-3 is used to enable the PS/2 mouse interrupt on IRQ 12 (refer to Chapter 2 for switch settings).

An Enhanced IDE hard drive interface is included on the SP. The IDE interface circuit on the board will support one or two IDE drives. The hard disk controller uses IRQ 14 for its interrupt. When adding an IDE drive to the board, the BIOS will auto-detect the new drive on boot. If the correct drive is not detected, use the BIOS to specify the hard drive parameters.

The SP contains a PC/AT compatible floppy disk controller. It is configured for industry standard single-speed floppy disk drives, and supports up to two of any combination of 5.25 or 3.5 inch drives. The BIOS setup program must be configured for the proper drives. The floppy controller uses IRQ 6 for its interrupt and DRQ 2 for its DMA channel. The floppy disk controller can be disabled in the Peripheral Management Setup section of the BIOS CMOS setup program.

Two serial ports and a parallel port are available on the SP processor board. One serial port is accessible through a standard DB-9 connector on the rear bracket (J8). The other serial port (COM2) and the parallel port (LPT1) are accessible internally through header connectors (J3 and J4). All ports comply fully with PC/AT interrupt and I/0 port standards. External access to the internal I/0 connectors (COM2 and LPT1) is accomplished through Cubix-supplied adapter boards.