BC Triton Series, Appendix A

As the system BIOS proceeds through its Power On System Test (POST), it displays an incrementing binary coded hexadecimal value using LEDs on the board (refer to the illustrations in Chapter 1 for LED location). If POST detects an error condition and comes to a halt, the LEDs display a value indicating the function currently under test. These codes are listed and defined in Tables A-1 and A-2, and can be used to troubleshoot a malfunctioning board.

An example of how the LED display appears when a POST error occurs is illustrated below. Error code "A7h" would appear as follows:

This display is addressed at I/O Port 80H and can be used after the operating system has booted for other display and debug purposes.

*Code*	*LED Display*	*Description*
C2	••xx xx•x	NMI is disabled. Power on delay is starting.
C5	••xx x•x•	Power on delay is completed. Disabling cache if any.
C6	••xx x••x	Calculating the ROM BIOS checksum.
C7	••xx x•••	ROM BIOS checksum passed. CMOS shutdown register test is to be performed next.
C8	••xx •xxx	CMOS shutdown register test is complete. The CMOS checksum calculation to be done next.
CA	••xx •x•x	CMOS checksum calculation is done, CMOS DIAG byte is written. Next, the CMOS status register is initialized for Date and Time.
CB	••xx •x••	CMOS initialization is complete. Any initialization required before the keyboard BAT is performed next.
CD	••xx ••x•	A BAT command to the keyboard controller is to be issued.
CE	••xx •••x	The keyboard BAT result was verified. Any initialization required after the keyboard controller BAT is performed next.
CF	••xx ••••	Initialization after the keyboard controller BAT is complete. A keyboard controller command byte code is to be written next.
D1	••x• xxx•	The keyboard controller command byte has been written. To check the INS key when pressed during power on.
D2	••x• xx•x	Check of INS key when pressed during power on was done. To disable DMA and Interrupt controllers.
D3	••x• xx••	DMA controller #1 and #2 disabled. Interrupt controller #1 and #2 disabled. Chipset initialization and auto memory detection about to begin.
D4	••x• x•xx	Chipset initialization and auto memory detection are done. To decompress the RUNTIME code.
D5	••x• x•x•	The RUNTIME code is decompressed.
DD	••x• ••x•	Transferring control to decompressed code in shadow RAM at F000:FFF0.
01h	xxxx xxx•	Processor register test about to start. NMIs are disabled next.
02h	xxxx xx•x	NMIs are disabled. The "power on" delay is starting.
03h	xxxx xx••	Power on delay has been completed. Intializations required before the keyboard BAT is done are now in progress.
04h	xxxx x•xx	The initializations required before the keyboard BAT are completed. Reading the keyboard SYS bit to check for soft reset or power-on next.
05h	xxxx x•x•	The soft reset or power-on setting has been determined. Next, enabling the ROM and disabling shadow RAM and Cache Memory, if any.
06h	xxxx x••x	ROM is enabled. Calculating the ROM BIOS checksum and waiting for the keyboard controller input buffer to be free.
07h	xxxx x•••	The ROM BIOS checksum test passed and the keyboard controller input buffer is free. Issuing a BAT command to the keyboard controller next.
08h	xxxx •xxx	A BAT command has been issued to the keyboard controller. Verifying the BAT command next.
09h	xxxx •xx•	The keyboard controller BAT result was verified. A keyboard controller command byte is to be written next.
0Ah	xxxx •x•x	A keyboard controller command byte code has been issued. Writing the command byte data next.
0Bh	xxxx •x••	The keyboard controller command byte has been written. Issuing the Pin 23, 24 blocking and unblocking command next.
0Ch	xxxx ••xx	Pin 23,24 of the keyboard controller has been blocked and unblocked. The keyboard controller NOP command is issued next.
0Dh	xxxx ••x•	The keyboard controller NOP command processing is done. The CMOS RAM shutdown register test is performed next.
0Eh	xxxx •••x	The CMOS RAM shutdown register Read/Write test passed. Calculating the CMOS RAM checksum and updating the DIAG byte next.
0Fh	xxxx ••••	The CMOS RAM checksum calculation is done and the DIAG byte is written. CMOS RAM initialization begins next if CMOS RAM is to be initialized during every boot.
10h	xxx• xxxx	CMOS RAM initialization (if any) is done. Next, the CMOS RAM status register is initialized for Date and Time.
11h	xxx• xxx•	The CMOS RAM status register has been initialized. Disabling the DMA and interrupt controllers next.
12h	xxx• xx•x	DMA controllers 1 and 2 and interrupt controllers 1 and 2 are disabled. Disabling the video display and initializing port B next.
13h	xxx• xx••	The video display is disabled and port B is initialized. Chipset initialization and auto memory detection are about to begin.
14h	xxx• x•xx	Chipset initialization and auto memory detection are done. The 8254 Channel 2 timer test is about to start.
15h	xxx• x•x•	The 8254 Channel 2 timer test is half-completed. The entire 8254 Channel 2 timer test is completed next.
16h	xxx• x••x	The entire 8254 Channel 2 timer test is done. The 8254 Channel timer test is done next.
17h	xxx• x•••	The 8254 Channel 1 timer test is done. The 8254 Channel 0 timer test is completed next.
18h	xxx• •xxx	The 8254 Channel 0 timer test is done. About to start memory refresh.
19h	xxx• •xx•	Memory refresh has been started. The memory refresh test is performed next.
1Ah	xxx• •x•x	The memory refresh line is toggling. Checking the 15 second ON/OFF time next.
1Bh	xxx• •x••	The memory refresh test has been completed. The base 64 KB memory test is about to start.
20h	xx•x xxxx	The base 64 KB memory test has been started. The address line test is to be done next.
21h	xx•x xxx•	The address line test passed. Toggling parity next.
22h	xx•x xx•x	The parity toggle has been completed. Performing a sequential data read/write test next.
23h	xx•x xx••	The base 64 KB sequential data read/write test passed. Performing any necessary system initialization before interrupt vector initialization.
24h	xx•x x•xx	The system configuration required before vector initialization has been completed. Interrupt vector initialization is about to begin.
25h	xx•x x•x•	Interrupt vector initialization is done. Reading the input port of the 8042 for the turbo switch setting (if any).
26h	xx•x x••x	The input port of the 8042 has been read. Initializing global data for the turbo switch.
27h	xx•x x•••	Global data initialization is done. Initialization after the interrupt vector initialization will be done next.
28h	xx•x •xxx	Initialization after interrupt vector initialization is completed. Setting monochrome mode next.
29h	xx•x •xx•	Monochrome mode is set. Setting color mode next.
2Ah	xx•x •x•x	Color mode is set. Toggling parity before the optional Video ROM test next.
2Bh	xx•x •x••	Parity toggle completed. About to do any system initialization required before the video ROM check.
2Ch	xx•x ••xx	Initialization before video ROM control is done. Looking for video ROM next. Control passed to video ROM next.
2Dh	xx•x ••x•	The video ROM check is done. Next, do processing after the video ROM returns control.
2Eh	xx•x •••x	Finished processing after the video ROM had control. If an EGA or VGA adapter is not found, the display memory read/write test is next.
2Fh	xx•x ••••	No EGA or VGA adapter has been found. The display memory read/write test is about to begin.
30h	xx•• xxxx	The display memory read/write test passed. About to look for retrace check.
31h	xx•• xxx•	The display memory read/write test or retrace check failed. About to perform the alternate display memory read/write test.
32h	xx•• xx•x	The alternate display memory read/write test passed. About to look for alternate display retrace checking.
33h	xx•• xx••	The video display check is completed. Verification of the display type with switch setting and the actual adapter card is next.
34h	xx•• x•xx	Verification of the display adapter is done. The display mode is set next.
35h	xx•• x•x•	The display mode has been set. The BIOS ROM data area is about to be checked.
36h	xx•• x••x	The BIOS ROM data area check is completed. Setting the cursor for the Power-On message next.
37h	xx•• x•••	Cursor setting for the Power-On message is done. Displaying the Power-On message next.
38h	xx•• •xxx	The Power-On message has been displayed. Reading the new cursor position next.
39h	xx•• •xx•	The new cursor position has been read and saved. Displaying the BIOS Identification String next.
3Ah	xx•• •x•x	The BIOS Identification String has been displayed. Displaying the "Hit <DEL>..." message next.
3Bh	xx•• •x••	The "Hit <DEL> ..." message has been displayed. The virtual mode memory test is about to start.
40h	x•xx xxxx	Preparing the virtual mode test. Verify from display memory next.
41h	x•xx xxx•	Returned to POST after verifying from display memory. Preparing the descriptor tables next.
42h	x•xx xx•x	The descriptor tables have been prepared. Entering virtual mode for the memory test next.
43h	x•xx xx••	Entered virtual mode. Enabling interrupts for diagnostics mode next.
44h	x•xx x•xx	Interrupts are enabled if the diagnostics switch is on. Initializing data to check the memory wraparound at 0:0h next.
45h	x•xx x•x•	Data has been initialized for the memory wraparound check. Checking for memory wraparound at 0:0h and finding the total system memory size next.
46h	x•xx x••x	The memory wraparound test has been done. The memory size calculation has been done. About to write memory test patterns.
47h	x•xx x•••	The memory test patterns were written to extended memory. Writing patterns in conventional memory (first 640 KB) next.
48h	x•xx •xxx	The patterns to be tested were written to conventional memory. Finding the amount of memory below 1 MB next.
49h	x•xx •xx•	The amount of memory below 1 MB was found and verified. Finding the amount of memory above 1 MB next.
4Ah	x•xx •x•x	The amount of memory above 1 MB was found and verified. Performing the BIOS ROM data area check test next.
4Bh	x•xx •x••	The BIOS ROM data area check is done. Checking the Del key status and clearing the memory below 1 MB for a soft reset next.
4Ch	x•xx ••xx	The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next.
4Dh	x•xx ••x•	The memory above 1 MB has been cleared via a soft reset. Clearing the memory size next.
4Eh	x•xx •••x	The memory test has started. No soft reset was performed. About to display the first 64 KB memory test.
4Fh	x•xx ••••	The memory size display has started. This display is updated during the memory test. Running the sequential and random memory test.
50h	x•x• xxxx	The test of memory below 1 MB completed. Adjusting the memory size for relocation and shadowing next.
51h	x•x• xxx•	The memory size has been adjusted for memory relocation above 1 MB and shadowing options. The test of memory above 1 MB is next.
52h	x•x• xx•x	The test of memory above 1 MB has completed. Preparing for real mode next.
53h	x•x• xx••	The CPU registers have been saved, including the memory size. Entering real mode next.
54h	x•x• x•xx	Shutdown was successful and the CPU is in real mode. Restoring the registers saved during preparation for shutdown next.
55h	x•x• x•x•	The registers have been restored. Disabling the Gate A20 address line next.
56h	x•x• x••x	The Gate A20 address line was disabled successfully. Checking the BIOS ROM data area next.
57h	x•x• x•••	The BIOS ROM data area check is partially completed. Completing the BIOS ROM data area check next.
58h	x•x• •xxx	The BIOS ROM data area check has completed. Clearing the "Hit Del" message next.
59h	x•x• •xx•	The "Hit Del" message has been cleared. About to start the DMA and interrupt controller tests.
60h	x••x xxxx	The DMA page register test passed. About to verify from display memory.
61h	x••x xxx•	The display memory verification test is done. About to perform the DMA Controller 1 base register test.
62h	x••x xx•x	The DMA Controller 1 base register test passed. Performing the DMA Controller 2 base register test next.
63h	x••x xx••	The DMA Controller 2 base register test passed. Performing the BIOS ROM data area check next.
64h	x••x x•xx	The BIOS ROM data area check is partially done. The BIOS ROM data area check is completed next.
65h	x••x x•x•	The BIOS ROM data area check is done. Programming the DMA Controllers 1 and 2 next.
66h	x••x x••x	DMA Controller 1 and 2 programming was completed. Initializing the 8259 interrupt controller next.
67h	x••x x•••	The 8259 initialization is done. Starting the keyboard test next.
80h	•xxx xxxx	The keyboard test has started. Issuing the keyboard reset command next and clearing the output buffer.
81h	•xxx xxx•	The keyboard reset command completed successfully. Next, checking the stuck keys and issuing the interface test command if there was an error.
82h	•xxx xx•x	The keyboard controller interface test is done. About to write a command byte and initialize the circular buffer.
83h	xx•• xx••	The command byte has been written and the global data initialization is done. About to check for locked keys.
84h	x•xx x•xx	Lock key checking is done. About to check for a memory size mismatch with CMOS RAM data.
85h	x•x• •x•x	The memory size check has been completed. About to display a soft error and check for password or bypass Setup.
86h	x••x x••x	The password has been checked. About to do programming before Setup.
87h	x••• x•••	The programming before Setup has been completed. Calling the BIOS Setup program next.
88h	•xxx •xxx	Returned from the BIOS Setup program and cleared the screen. Programming after Setup.
89h	•xxx •xx•	The programming after Setup is completed. Displaying the Power-On screen message next.
8Ah	•xxx •x•x	The first screen message has been displayed. About to display the "Wait..." message.
8Bh	•xxx •x••	The "Wait..." message has been displayed. About to perform system and video BIOS shadowing.
8Ch	•xxx ••xx	System and video BIOS shadowing was successful. About to perform Setup options programming after Standard CMOS Setup.
8Dh	•xxx ••x•	The Setup options are programmed. The mouse check and initialization is done next.
8Eh	•xxx •••x	The mouse check and initialization is done. Checking the floppy disk next.
8Fh	•xxx ••••	The floppy disk check indicated that the floppy drive needs to be initialized. Floppy drive configuration is next.
90h	•xx• xxxx	Floppy drive configuration has completed. Hard disk configuration is next.
91h	•xx• xxx•	The hard disk presence test has completed. Hard disk configuration is next.
92h	•xx• xx•x	Hard disk configuration has completed. Checking the BIOS ROM data area next.
93h	•xx• xx••	The BIOS ROM data area check was partially completed. The entire BIOS ROM data area check is completed next.
94h	•xx• x•xx	The BIOS ROM data area check has fully completed. Setting the base and extended memory sizes next.
95h	•xx• x•x•	The memory size has been adjusted because of mouse support and hard disk type 47. Verifying from display memory next.
96h	•xx• x••x	Returned after verifying from display memory. Initializing before C8000h adapter ROM control next.
97h	•xx• x•••	Any initialization that had to be done before control is passed to the adapter ROM at C8000h option has been completed. The adapter ROM check and control test is next. Relinquishing control to adapter ROM at C8000h.
98h	•xx• •xxx	The adapter ROM control test has been done. About to do required processing after the adapter ROM returns control.
99h	•xx• •xx•	Any initialization for the option ROM test was done. Configuring the timer data area and the parallel printer base address next.
9Ah	•xx• •x•x	Set the timer data area and the parallel printer base address. Setting the RS-232 base address next.
9Bh	•xx• •x••	Set the RS-232 base address. Initializing before the coprocessor test next.
9Ch	•xx• ••xx	The required initialization before the coprocessor test has been done. Initializing the coprocessor next.
9Dh	•xx• ••x•	The coprocessor has been initialized. Performing any initialization after the coprocessor test next.
9Eh	•xx• •••x	Initialization after the coprocessor test is completed. Checking the Extended Keyboard, Keyboard ID and Num Lock keyboard settings next.
9Fh	•xx• ••••	The Extended Keyboard flags have been checked, the Keyboard ID flag set, and Num Lock is set On or Off as specified. The Keyboard ID command is issued next.
A0h	•x•x xxxx	The Keyboard ID command has been issued. The Keyboard ID flag reset is next.
A1h	•x•x xxx•	The Keyboard ID flag reset has been done. The cache memory tests follow.
A2h	•x•x xx•x	The cache memory test has been done. Displaying any soft errors next.
A3h	•x•x xx••	Soft error display is complete. Setting the keyboard typematic rate next.
A4h	•x•x x•xx	The keyboard typematic rate is set. Programming the memory wait states next.
A5h	•x•x x•x•	Memory wait states programming is done. The screen is cleared next.
A6h	•x•x x••x	The screen has been cleared. Enabling parity and NMIs next.
A7h	•x•x x•••	NMIs and parity have been enabled. Performing any initialization required before passing control to the adapter ROM at E0000h next.
A8h	•x•x •xxx	Initialization before E0000h adapter ROM control has been done. The E000h adapter ROM gets control next.
A9h	•x•x •xx•	Returned from E0000h adapter ROM control. Performing any initialization required after E0000h adapter ROM control next.
AAh	•x•x •x•x	Initialization after E0000h adapter ROM control has been done. Displaying the system configuration next.
D1	••x• xxx•	To copy any code to a specific area.
D0	••x• xxxx	The system configuration is displayed.
00h	xxxx xxxx	The system configuration has been displayed. Passing control to INT 19h Bootstrap Loader next.

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