BC 4035
Chapter 2 - Hardware

Configurable Hardware Options

The options described below are supported by the BC 4035 Series processors.

Ethernet

An Ethernet controller is integrated onto each BC Series processor. This controller is configured with hardware switches. Refer to Chapter 4 - Technical Reference for specific Ethernet configuration options.

Reset Loss of DCD / DSR

The BC Board can be configured to perform a hardware reset when the Data Carrier Detect (DCD) or Data Set Ready (DSR) signal changes from true to false on the COM1 serial port. This feature is designed for use in remote communication applications where the BC is used to host dial in session on a network, as it forces the BC host to reset after each dial in session. The reset causes the BC hardware to return to its initial state and also prevents the next dial in user from accessing data left in memory by the previous user. This function is available on COM1 only.

Video

A hardware switch can be set to disable the on board video controller. If this controller is disabled, an external video controller with a video BIOS at address C0000 hexadecimal must be installed. Refer to Chapter 4 - Technical Reference for information on resolution support.

Cubix Supervisory System

Cubix offers an optional Supervisory System for BC processor management. The Supervisory System requires installation of an IES (Intelligent Environmental Sensor) module in each Cubix subsystem being supervised. This IES module communicates with the BC processors in the subsystem via a hardware interrupt which is configurable as IRQ 10 or IRQ 15 on each BC. If no IES is installed, configure the BC for no Cubix Supervisory interrupt. In older subsystems this interrupt should be configured for the PA 3030 supervisory processor (the PA 3030 was the predecessor to IES).

Mouse

A PS/2 style mouse port is included on each BC processor. The mouse may be connected to the BC via a Cubix multiplexor or by installing an adapter (refer to Chapter 3 - Installation). If a mouse is installed, the mouse interrupt (IRQ 12) must be enabled in the hardware configuration. The "Mouse Support Options" in the Advanced CMOS Setup section of the BIOS Setup Utilities must be "Enabled" (refer to the American Megatrends, Inc. BIOS Configuration Program User’s Guide).

Switch and Jumper Settings

For an explanation of the features controlled by the BC 4035 switch settings, refer to Chapter 4 - Technical Reference.

Figure 2 - 1, BC 4035 Board

BC4035A

The BC 4035A is an updated version of the BC 4035. It provides support for 3.5 volt processors, such as the 80486DX4 running at 100 MHz and some 80486DX2 66MHz processors. The BC 4035A also includes local bus video and support for EIDE hard disk drives over 540MB. To identify the board type, refer to the label on the back side of the board. "BC 4035" or "BC 4035A" is silk screened on the upper left corner when the ISA edge connectors are pointing down. The type of board is also displayed in the sign-on message when the board is booted.

Table 2 - 1
BC 4035 Reset on Loss of DCD or DSR (Switch S1)

Table 2 - 2
BC 4035 Switch S2 Summary

Jumpers JP1, JP3, and JP4 configure the BC 4035 for the type of CPU installed. JP2 is a pair of pads which when shorted together with power off will clear the CMOS RAM. This may be necessary if a password has been entered and later forgotten.

Table 2 - 3
BC 4035 JP1, JP3 - Processor Speed Select

Warning! P1 and JP3 are configured at the factory for the CPU type installed and should not be changed

Table 2 - 4
BC 4035 JP4 - Processor Type

I/O Connections

I/O connections on the BC on the Cubix enclosure in which the processor is installed. The headers and connectors on the BC should be connected to the device indicated for the appropriate enclosure in Table 2-5.

Table 2 - 5
Cubix Enclosure I/O Connections - BC 4035

*When the BC is installed in an old Cubix subsystem (ERS, ERS/FT or MultiServ/FT), the reset, speaker, supervisory interface, mouse, video and keyboard signals are interfaced to the multiplexor via headers J4, J5, J6, J9 and J10. In an ERS II, ERS/FT II, PowerSMP, or BOS subsystem, these signals are combined into the single J3 header. Refer to Figure 2 - 1 for connector locations.

Specifications - BC 4035

Processor

Bus

Real Time CMOS Clock

Memory Support

Video Support

Keyboard/Mouse Support

Communication Ports

Disk Support

Ethernet Port

Line Busy

Other Input/Output

Communications Processor Characteristics

Power

Environmental

Physical Measurements

Warranty

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