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QL 3002
Quick Reference Guide
This header requires a optional I/O adapter from Cubix. Attempting to connect a device directly to this connector will damage the board.
This header requires a optional I/O adapter from Cubix. Attempting to connect a device directly to this connector will damage the board. The pinout listed below is for the connectors on the optional video/inout diagnostic board. It connects to the QL 3002 board with a ribbon cable to J1 or J3.
VGA Video (DB15)
| 1 | Red | 9 | n/c |
| 2 | Green | 10 | Ground |
| 3 | Blue | 11 | n/c |
| 4 | n/c | 12 | n/c |
| 5 | Ground | 13 | Vsync |
| 6 | Ground | 14 | Hsync |
| 7 | Ground | 15 | n/c |
| 8 | Ground |
Keyboard (6 pin mini-din)
| 1 | Data |
| 2 | n/c |
| 3 | Ground |
| 4 | +5V |
| 5 | Clock |
| 6 | n/c |
Each QL 3002 board houses a seven position DIP switch (SW1). Switch 1 selects the base l/O address used by the server driver to communicate with the QL 3000 processors. The QL interface requires eight consecutive l/O ports beginning with the base l/O address. The l/O addresses selected must not be assigned to any non QL 3000 Series devices installed in the file server or bridge hosting the QL 3000 Series boards. However, all of the QL 3000 Series boards installed in this host should have the same base l/O address.
| Address (hex) | SW1-1 | SW1- 2 |
| 220 | ON | ON |
| 230 | ON | OFF |
| 320 | OFF | ON |
| 330 | OFF | OFF |
The QL 3002 is typically connected via a COM port to a modem performing remote communications over a telephone line. The COM port monitors the state of the Data Carrier Detect (DCD) or Data Set Ready (DSR) signals coming from the modem. The QL processors can be configured to perform an automatic hardware reset if DCD or DSR is dropped. One practical usage of this feature is to force the QL processor to reset between remote sessions. This ensures users that they are connecting to a newly initialized system. It also verifies that users are properly disconnected from the network when their session terminates (i.e., a user will not remain logged into NetWare after "hanging up" the phone). Depending upon the system configuration, either DCD or DSR will indicate that the telephone signal connection is established and that the modem is ready. Most configurations support DCD. However, if a multiplexer is installed between the QL 3002 COM port and the modem, it may be necessary to monitor DSR instead. Refer to the multiplexer manufacturer's documentation for this information. The QL 3002 contains a seven position DIP switch (SW1 ) that configures this feature.
| Switch | Description | Switch ON | Switch OFF |
| 3 | Selects COM port for both processors | COM1 | COM2 |
| 4 | Selects signal to be monitored for both processors | DCD | DSR |
| 5 | Enable/Disable reset on processor A | Enable | Disable |
| 6 | Enable/Disable reset on processor B | Enable | Disable |
Each node on a Novell network must be identified by a unique address. This address consists of two parts: a network number and a node number. When the Cubix server driver is installed, it must be assigned a unique network number. Each QL 3000 Series node to be supported by the server driver must be assigned a unique node number. The node number is selected by a DIP switch (SW2) on the QL 3002 board. Valid node numbers range from 2 to 249. It is recommended that the QL 3002 node numbers be assigned consecutively beginning with node number 2 as this will maximize network performance.
The QL 3002 board uses a seven position DIP switch to select its node numbers. Since the QL 3002 contains two nodes, these seven switches determine the seven high order bits of the address for each node. The low order bit for the Port A node is assumed to be 0, while it is assumed to be 1 for the Port B node. A switch is OFF when its handle is away from the board.
| # | Switch SW1 | # | Switch SW1 | # | Switch SW1 |
| 002 | 7 off | 052 | 2,4,7 off | 0A2 | 1,3,7 |
| 004 | 6 | 054 | 2,4,6 | 0A4 | 1,3,6 |
| 006 | 6,7 | 056 | 2,4,6,7 | 0A6 | 1,3,6,7 |
| 008 | 5 | 058 | 2,4,5 | 0A8 | 1,3,5 |
| 00A | 5,7 | 05A | 2,4,5,7 | 0AA | 1,3,5,7 |
| 00C | 5,6 | 05C | 2,4,5,6 | 0AC | 1,3,5,6 |
| 00E | 5,6,7 | 05E | 2,4,5,6,7 | 0AE | 1,3,5,6,7 |
| 010 | 4 | 060 | 2,3 | 0B0 | 1,3,4 |
| 012 | 4,7 | 062 | 2,3,7 | 0B2 | 1,3,4,7 |
| 014 | 4,6 | 064 | 2,3,6 | 0B4 | 1,3,4,6 |
| 016 | 4,6,7 | 066 | 2,3,6,7 | 0B6 | 1,3,4,6,7 |
| 018 | 4,5 | 068 | 2,3,5 | 0B8 | 1,3,4,5 |
| 01A | 4,5,7 | 06A | 2,3,5,7 | 0BA | 1,3,4,5,7 |
| 01C | 4,5,6 | 06C | 2,3,5,6 | 0BC | 1,3,4,5,6 |
| 01E | 4,5,6,7 | 06E | 2,3,5,6,7 | 0BE | 1,3,4,5,6,7 |
| 020 | 3 | 070 | 2,3,4 | OCO | 1,2 |
| 022 | 3,7 | 072 | 2,3,4,7 | 0C2 | 1,2,7 |
| 024 | 3,6 | 074 | 2,3,4,6 | 0C4 | 1,2,6 |
| 026 | 3,6,7 | 076 | 2,3,4,6,7 | 0C6 | 1,2,6,7 |
| 028 | 3,5 | 078 | 2,3,4,5 | 0C8 | 1,2,5 |
| 02A | 3,5,7 | 07A | 2,3,4,5,7 | 0EC | 1,2,5,7 |
| 02C | 3,5,6 | 07C | 2,3,4,5,6 | 0CC | 1,2,5,6 |
| 02E | 3,5,6,7 | 07E | 2,3,4,5,6,7 | 0CE | 1,2,5,6,7 |
| 030 | 3,4 | 080 | 1 | 0D0 | 1,2,4 |
| 032 | 3,4,7 | 082 | 1,7 | 0D2 | 1,2,4,7 |
| 034 | 3,4,6 | 084 | 1,6 | 0D4 | 1,2,4,6 |
| 036 | 3,4,6,7 | 086 | 1,6,7 | 0D6 | 1,2,4,6,7 |
| 038 | 3,4,5 | 088 | 1,5 | OD8 | 1,2,4,5 |
| 03A | 3,4,5,7 | 08A | 1,5,7 | ODA | 1,2,4,5,7 |
| 03C | 3,4,5,6 | 08C | 1,5,6 | ODC | 1,2,4,5,6 |
| 03E | 3,4,5,6,7 | 08E | 1,5,6,7 | ODE | 1,2,4,5,6,7 |
| 040 | 2 | 090 | 1,4 | 0E0 | 1,2,3 |
| 042 | 2,7 | 092 | 1,4,7 | 0E2 | 1,2,3,7 |
| 044 | 2,6 | 094 | 1,4,6 | 0E4 | 1,2,3,6 |
| 046 | 2,6,7 | 096 | 1,4,6,7 | 0E6 | 1,2,3,6,7 |
| 048 | 2,5 | 098 | 1,4,5 | OE8 | 1,2,3,5 |
| 04A | 2,5,7 | 09A | 1,4,5,7 | OEA | 1,2,3,5,7 |
| 04C | 2,5,6 | 09C | 1,4,5,6 | OEC | 1,2,3,5,6 |
| 04E | 2,5,6,7 | 09E | 1,4,5,6,7 | OEE | 1,2,3,5,6,7 |
| 050 | 2,4 | 0A0 | 1,3 | OFO | 1,2,3,4 |
The QL 3002 is equipped with a minimum of 4 MB of RAM per processor. The QL 3002 RAM resides in standard PS\2 type 72-pin SlMMs. One SIMM may be installed per processor.
| F800-FFFF | Reserved for ROM BIOS, must be excluded from use by all memory managers. |
| F000-F7FF | Available for use as Upper memory (UMB). |
| EE00-EFFF | Reserved for network controller RAM. Must be excluded from use by all memory managers. |
| C800-EDFF | Available for use as Expanded (EMS) or Upper Memory (UMB). |
| C000-C7FF | Reserved for VGA BIOS |
| B800-BFFF | VGA/CGA Video Memory |
| B000-B7FF | VGA/Mono Video Memory |
| A000-AFFF | VGA Video Memory |
| 0000-9FFF | Conventional DOS |
| 000 - 00F | DMA 1 |
| 020 - 021 | PIC 1 |
| 040 - 043 | Timer |
| 060,064 | 8742 Keyboard Controller |
| 061 | Port B |
| 070 - 071 | CMOS RAM & NMI Mask Register |
| 080 | Manufacturing Hex Display |
| 081 - 08F | DMA Page Registers |
| 0A0 - 0A1 | PIC 2 |
| 0C0 - 0DF | DMA 2 |
| 2F8 - 2FF | COM 2 |
| 300 - 302 | QL 3002 Command/Status |
| 378 - 37F | LPT 1 |
| 3B0 - 3DF | VGA |
| 3F8 - 3FF | COM 1 |
| 46E8,102 | VGA Configuration Ports |
Interrupt Channels
| NMI | Parity/VGA |
| 0 | Timer |
| 1 | Keyboard |
| 2 | Cascaded Input for PIC 2 |
| 3 | COM 2 |
| 4 | COM 1 |
| 5 | Broadcast Interrupt from Fileserver |
| 6 | Transmit Interrupt from Fileserver |
| 7 | LPT 1 |
| 8 | Real Time Clock |
| 9 | VGA |
| 10 | Receive Interrupt from Fileserver |
| 11 | Not Used |
| 12 | Not Used |
| 13 | Numeric Co-Processor Interrupt |
| 14 | Not Used |
| 15 | Not Used |
No DMA channels are used by the QL 3002.
This document, and all Web contents, Copyright © 1997 by Cubix Corp., Carson City, NV, USA.
