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M1 SCHEMATIC ON PAGE 11 PIN CONFIGURATION U3-801895-02 ACIA SYNERTEK SYP6551A 2 MHz	TRANSMIT/RECEIVE CHARACTERISTICS CHARACTERISTICS SYM -02 2 MHZ UNIT MIN MAX TRANSMIT/RECEIVE CLOCK RATE tCCY * 400 - ns TRANSMIT/RECEIVE CLOCK HIGH TIME tCH 175 - ns TRANSMIT/RECEIVE CLOCK LOW TIME tCL 175 - ns XTL1 TO TXD PROPAGATION DELAY tDD - 500 ns RTS PROPAGATION DELAY tDLY - 500 ns IRQ PROPAGATION DELAY (CLEAR) tIRQ - 500 ns (tr, tf = 10 to 30 ns) *The Baud Rate with External Clocking is: BAUD RATE 1   --------------   16 x TCCY
PIN CONFIGURATION U19-251641-02 PLA	CS R/W D0-D7 L L DATA BUS TO PORT L H PORT TO DATA BUS H X ISOLATION L = LOW LEVEL H = HIGH LEVEL X = IRRELEVANT	PIN CONFIGURATION
	MOS 6529B 3 MHz
	U5/U27-251640-03 SINGLE PORT INTERFACE

Plus 4 Schematic #310164 (2 of 4)

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This page has been created by Sami Rautiainen.
Read the small print.	Last updated August 16, 1998.