2031 LP CIRCUIT THEORY

The Clock Circuits

Crystal Y1 outputs a 16 MHz clock signal. This is input to UC6 on pin 8. UC6 is configured as a - 16 frequency divider. The output of UC6 pin 12 is a 1 MHz clock signal used as the system clock (Phase 0) for the microprocessor. UE7 is a programmable counter (÷ 16, ÷ 15, ÷ 14, ÷: 13) that outputs a varying frequency clock used to compensate for difference in recording area/sector for sectors on inner tracks (Trks 1, 2,3) as compared to sectors on out most tracks (Trks 33,34,3 5). The area/sector for inner tracks is less than the area/sector for out most tracks, so the recording clock frequency is increased when writing on inner tracks to keep the flux density constant. This clock output is on pin 12 of UE7.

Tracks	Clock Frequency	Divide By
1-17	1.2307 MHz	13
18-24	1.1428 MHz	14
25-30	1.0666 MHz	15
31-35	1 MHz	16

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This page has been created by Sami Rautiainen.
Read the small print.	Last updated December 02, 1998.