Commodore 2031 Service Manual: 2031 HP Circuit Theory

2031 HP CIRCUIT THEORY

IEEE Interface

All of the signals on the interface are controlled by the I/O device U3H. Eight parallel bi-directional data lines, PA0-PA7, are used as the parallel data bus for the interface. U1S is an octal bus transceiver used to provide communication on the general purpose interface bus, GPIB, between operating units of the system. The data transfer and bus-management signals are communicated by U1A, thus completing the 16-line interface of the IEEE-488 bus.

DAV	Data Valid	DAV low signifies data is valid on the data bus.
EOI	End or Identity	CBM always sets EOI low while the last data byte is being transferred.
DAC	Data Not Accepted	DAC is low when data is being read and returned high after the last data byte is read.
RFD	Not Ready For Data	RFD is low until all receivers are ready to accept data, then the line will go high.
SRQ	Service Request	Not implemented in BASIC but available to the CBM user.
ATN	Attention	The host sets the signal low while sending commands on the data bus.
REN	Remote Enable	REN is held low by the bus controller and the host has this pin permanently grounded.
IFC	Interface Clear	The host sends its internal reset signal as IFC low to initialize all devices.

Reset Logic

The 2031 disk drive is automatically reset on power up by U3S, a 555 timer, when triggered by the 5V applied at pin 8. A reset can also be set by the IFC line on the IEEE interface. The output pulse width is determined by the values of R43 and C36. The pulse width = 1.1 x R43 x C36 = 1 second. The output on pin 3 of U3S, is an active "high". It is inverted by U3A to active "low". A low output at WA pin 2, resets the unit and initializes all of the microprocessor logic.

This page has been created by Sami Rautiainen.
Read the small print.	Last updated November 16, 1998.